1. Field of the Invention
The invention relates to a tag controller for controlling cache memory data access of a cache memory module, more particularly to a non-stalling pipeline tag controller which is capable of handling consecutive cache tag accesses from an external input unit and which can be updated without stalling.
2. Description of the Related Art
In a computer system, a cache memory system is commonly employed to store selected memory data for ready access by a processor. The cache memory system generally includes a cache random-access-memory module or data RAM for storing the memory data, and a tag controller that includes a tag RAM and associated control logic for the tag RAM. The tag RAM stores indices or tags to the memory data in the data RAM. A xe2x80x9ccache hitxe2x80x9d occurs when the desired memory data resides in the cache memory system, whereas a xe2x80x9ccache missxe2x80x9d occurs when the desired memory data does not reside in the cache memory system.
The actual transfer of data between the cache memory system and the processor is often conditioned by the results of a cache tag look-up. Minimizing cache storage latency is particularly challenging in that the processor must often stall until cache access has been validated. In addition, all cache data modifications must be reflected in the states of the tags in the tag RAM to maintain cache consistency.
FIG. 1 illustrates a conventional tag controller 1 with a pipeline architecture. The conventional tag controller 1 includes a tag register 10, an address register 11, a write register 12, a tag RAM 13, a comparator 14, and an arbitrator 15. An external input unit 2 is coupled to the tag controller 1 and provides an input tag and an index address during a cache tag access operation. The input tag is stored in the tag register 10, whereas the index address is stored in the address register 11. The tag RAM 13 outputs one of the tags stored therein according to the contents of the address register 11. The comparator 14 compares the output of the tag RAM 13 with the contents of the tag register 10. When a match is detected, the comparator 14 provides a xe2x80x9chitxe2x80x9d signal to the arbitrator 15. The arbitrator 15 responds by providing a control signal to the data RAM (not shown) so do to enable access to the desired memory data. When a match is not detected, the comparator 14 provides a xe2x80x9cmissxe2x80x9d signal to the arbitrator 15. At this time, the arbitrator 15 performs an updating operation during a subsequent clock cycle, wherein the arbitrator 15 loads the contents of the tag register 10 during the previous clock cycle into the write register 12 and stores a replacement address into the address register 11. The input update tag from the external input 2 can thus be stored in a location of the tag RAM 13 specified by the replacement address.
From the foregoing, it is evident that the conventional tag controller 1 has the following pipeline stages: storage of an input tag; access of the tag RAM 13; comparison of tags; and arbitration of the replacement address and updating of the tag RAM 13. However, updating of the tag RAM 13 can cause stalling in the pipeline of the conventional tag controller 1. Because the tag RAM 13 has a single port, simultaneous read and write conflict must be avoided, thereby necessitating stalling for rearranging the read and write operations to ensure access of the tag RAM 13 at different times. Furthermore, because updating of the tag RAM 13 is deferred several cycles by the pipeline stages, subsequent tag requests should wait until the tag RAM 13 has been validated.
Therefore, the object of the present invention is to provide a non-stalling pipeline tag controller which is capable of handling consecutive cache tag accesses from an external input unit and which can be updated without stalling.
According to the present invention, a non-stalling pipeline tag controller is adapted to handle consecutive cache tag accesses from an external input unit and to control cache memory data access of a data memory module. The non-stalling pipeline tag controller comprises a source register, a holding register, a tag memory module, a status module and an arbitration module.
The source register is adapted to be coupled to the external input unit so as to receive and store a first source tag therefrom during a first clock cycle and so as to receive and store a second source tag therefrom during a second clock cycle.
The holding register is coupled to the source register. The holding register receives and stores the first source tag from the source register during the second clock cycle, and receives and stores the second source tag from the source register during a third clock cycle. The holding register is adapted to be coupled to the data memory module so as to provide the first source tag thereto during the third clock cycle.
The tag memory module includes a tag memory unit for storing tags to memory data in the data memory module. The tag memory unit is coupled to the holding register. The tag memory module further includes a first comparator unit coupled to the tag memory unit and the source register. The first comparator unit generates a first decision signal to indicate whether the source tag in the source register matches with one of the tags in the tag memory unit.
The status module includes a second comparator unit coupled to the source and holding registers. The second comparator unit generates a second decision signal to indicate whether the source tags stored in the source and holding registers match with one another. The status module further includes a decision unit coupled to the first and second comparator units. The decision unit compares the first and second decision signals and generates a third decision signal to indicate to occurrence of a cache hit or cache miss condition according to result of comparison made by the decision unit.
The arbitration module is coupled to the decision unit and the tag memory module. The arbitration module generates a control signal adapted to be provided to the data memory module so as to enable access to the data memory module according to the source tag from the holding register upon detection of the occurrence of the cache hit condition. The arbitration module generates a replacement address that is provided to the tag memory module so as to enable storage of the source tag from the holding register in the tag memory unit according to the replacement address in order to update contents of the tag memory unit upon detection of the occurrence of the cache miss condition.